1. Field of the Invention
The present invention relates to a technology concerning complementary metal-oxide-semiconductor (CMOS) devices, and particularly to a method for gate leakage reduction and Vt shift control for a CMOS device and a CMOS device made by such method.
2. Description of the Prior Art
Along with MOS device miniaturization, gate dielectric has been scaled aggressively, but gate leakage will be increased while gate dielectric thickness is thinning down. Nitride dose of SiON gate dielectric is increased through a decoupled-plasma nitridation (DPN) treatment to meet the demand of thin gate dielectric with low gate leakage. In other words, the DPN process is used to improve robustness of ultra thin gate dielectrics and to efficiently reduce the gate leakage, as well as to offer a better barrier to boron. However, high nitride dose of SiON gate dielectric will lead the threshold voltage, Vt, of NMOS or PMOS to seriously shift. There are several researches using fluorine implantation after the deposition of polysilicon gate electrode to suppress the side effect, Vt shift.
In other respect, U.S. Pat. No. 6,358,865 discloses a process for the oxidation of a substrate and the formation of oxide regions in the substrate by implantation of fluorine into the silicon lattice and subsequently forming an oxide region by a typical oxide growth process, such as thermal oxidation process. The growth of the oxide region depends on the amount of fluorine implanted into the substrate, the depth which the fluorine is implanted and the energy at which the fluorine is implanted. Therefore, a desired thickness of the oxide region can be obtained by controlling these factors. Furthermore, the process allows for the simultaneous growth of oxides having different thicknesses at the same time. For example, a region having fluorine implanted forms a thick oxide region to serve as a field oxide, and a predetermined region for gate oxide is not implanted with fluorine and will form a thin oxide layer simultaneously to serve as a gate oxide. Issues regarding gate leakage reduction and Vt shift control are not discussed therein.
Suppressing the shift of high nitride dose SiON gate Vt by fluorine implantation after poly-silicon gate electrode deposition is dramatic. Unfortunately, the fluorine implantation after polysilicon gate electrode deposition induces a new problem, that is, the difference between the equivalent oxide thickness (EOT) of the gate dielectric layers of the PMOS transistor and the EOT of the gate dielectric layer of the NMOS transistor will increase with the increase of fluorine implantation after polysilicon gate electrode deposition.
Therefore, there is still a need for a novel method to reduce gate leakage and control Vt, especially in the 45 nm or beyond the technology node.